Tag Archives: cadence vcs hdl_path verilog

hdl_what?() – Tale Of Verilog Array

Suppose we have an old eVC, that covers some RTL aspect.
As life go on, the RTL now has multiple instances, so we need to have an array of eVCs.

We just have to update the simple ports connection:
keep nice_evc.nice_port.hdl_path() == appendf("nice_rtl.nice_array[%d]", agent_num);

So simple…

Well, working with VCS simulator, this simple syntax just works.

However, lately I’m trying to migrate my environment unto Cadence IES.

(There were several issues in the process, and Cadence support were very helpful.)

One interesting issue was with my “nice array”.
It appears that IES just didn’t like this declaration.
Cadence suggested switching the simple_port to indexed port.
This could have been a solution – but it required changing the legacy eVC…

After some investigations, it appears that the solution is using both hdl_path() and hdl_expression(), like this:
keep nice_evc.nice_port.hdl_path() == "nice_rtl.nice_array";
keep nice_evc.nice_port.hdl_expression() == appendf("%s, nice_rtl.nice_array[%d]", full_hdl_path(), agent_num);

Pay attention that hdl_expression() isn’t aware of hdl_path() hierarchy tree. I solved this by prepending full_hdl_path().

To be honest, I still don’t understand the problem, but at least we have a solution 🙂


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